Systematic Design of Analog IP Blocks

Systematic Design of Analog IP Blocks introduces a design methodology that can help to bridge the productivity gap.



The ever-decreasing feature size has continuously provided improved functionality at a reduced cost. As the feature size decreased, designs moved from digital microprocessors and application specific integrated circuits (ASICs) to systems-on-a-chip (SoC). The design capabilities of the designer however, have not been increased equally. Analog design tools are only just emerging, and the design of the small analog part in the hostile digital environment, has become a tremendous bottleneck. This text introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified: commodity IP and star IP. Each category requires a different approach to boost design productivity. Commodity IP blocks are well suited to be automated in an analog synthesis environment and provided as soft IP. The design knowledge is usually common knowledge, and reuse is high accounting for the setup time needed for the analog library. Star IP still changes as technology evolves and the design cost can only be reduced by following a systematic design approach supported by point tools to relieve the designer from error-prone, repetitive tasks, allowing him/her to focus on new ideas to push the limits of the design. To validate the presented methodologies, three different industrial-strength applications have been selected and designed accordingly. Firstly, a particle detector front-end for space applications has been designed and embedded in the AMGIE library for further re-use. Performance compares favourably to an earlier manual design. Starting from specification, a physical layout can be generated within a few days. Secondly, current-steering D/A converters have been selected as a test-engine for the design methodology of Star IP. A novel topology has been developed allowing full flexibility to the designer in terms of switching scheme. This allows the designer to implement the Q2 Random Walk switching scheme which averages out random and systematic errors resulting in the first intrinsic 14-bit linear D/A converter in CMOS technology. The overall design time was reduced from 11 to four weeks. A third and final test-case, an 8 bit 200MS/s interpolating/averaging A/D converter has been designed. Performance and design times compare favorably to an earlier manual design. All experiments prove that despite general disbelieve, design cost can be reduced considerably, without compromising performance, by adopting the proper design methodology.