Design for Yield and Reliability for Nanometer CMOS Digital Circuits Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits

Name: Design for Yield and Reliability for Nanometer CMOS Digital Circuits
Author: Mostafa Hassan

Auteur: Mostafa Hassan

Taal: Engels

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Design for Yield and Reliability for Nanometer CMOS Digital Circuits

Auteur: Mostafa Hassan Anis Mohab

Uitgever: Lap Lambert Academic Publishing

Co-auteur: El-Masry Mohamed

Engels
Paperback
9783659513619
januari 2014
296 pagina's

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Samenvatting

The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 40 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield and reliability of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops.

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Taal: Engels
Bindwijze: Paperback
Verschijningsdatum: 2014-01-26
Aantal pagina's: 296 pagina's
Illustraties: Met illustraties

Betrokkenen

Auteur: Mostafa Hassan Anis Mohab
Co-auteur: Anis Mohab
Uitgever: Lap Lambert Academic Publishing

EAN

EAN: 9783659513619

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Extra groot lettertype: Nee
Oorspronkelijke releasedatum: 2014-01-26
Subtitel: Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits
Thema Subject Code: TJF