Designing Reliable and Efficient Networks on Chips
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- Engels
- Hardcover
- 9781402097560
- 21 april 2009
- 198 pagina's
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Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge.
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
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Inhoud
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- en
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- Hardcover
- Oorspronkelijke releasedatum
- 21 april 2009
- Aantal pagina's
- 198
- Illustraties
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- Hoofdauteur
- Srinivasan Murali
- Hoofduitgeverij
- Springer-Verlag New York Inc.
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- 2009 ed.
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- 159 mm
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- 235 mm
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- 159 mm
- Verpakking hoogte
- 19 mm
- Verpakking lengte
- 235 mm
- Verpakkingsgewicht
- 454 g
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- 9781402097560
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