Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
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Auteur:
Pascal Meinerzhagen
Adam Teman
- Engels
- Paperback
- 9783319868554
- 12 mei 2018
- 146 pagina's
Samenvatting
Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
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Inhoud
- Taal
- en
- Bindwijze
- Paperback
- Oorspronkelijke releasedatum
- 12 mei 2018
- Aantal pagina's
- 146
- Illustraties
- Nee
Betrokkenen
- Hoofdauteur
- Pascal Meinerzhagen
- Tweede Auteur
- Adam Teman
- Co Auteur
- Robert Giterman
- Hoofduitgeverij
- Springer International Publishing Ag
Overige kenmerken
- Editie
- Softcover reprint of the original 1st ed. 2018
- Extra groot lettertype
- Nee
- Product breedte
- 155 mm
- Product lengte
- 235 mm
- Studieboek
- Ja
- Verpakking breedte
- 155 mm
- Verpakking hoogte
- 235 mm
- Verpakking lengte
- 235 mm
- Verpakkingsgewicht
- 2467 g
EAN
- EAN
- 9783319868554
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